Three-dimensional thermal investigations at board level in a reflow oven using thermal-coupling method

Purpose - The purpose of this paper is to develop thermal modelling to investigate the thermal response of sample boards (at board level) during the preheating stage of the reflow process and to validate with experimental measurements. Design/methodology/approach - A thermal-coupling method that adopted the Multi-physics Code Coupling Interface (MpCCI) was utilized. A forced-convection reflow oven was modelled using computational fluid dynamic software (FLUENT 6.3.26), whereas structural heating at the board level was conducted using finite-element method software (ABAQUS 6.9). Findings - The simulation showed a complex flow pattern having characteristics of a free-jet region, stagnation-flow region, wall jet-region, recirculation region and vortices. A sharp maximum heat-transfer coefficient was detected in the stagnation region of the jet, resulting in a spatial variation of local heat transfer on a thermal profile board (TPB). This coefficient affected the temperature distribution in the TPB with different specific heat capacitances and thermal conductivity of the structure. The simulation results were in good agreement with the experimental data and analytical model. The cold region and temperature uniformity (Delta T) increased with increasing complexity of the TPB. The cold region can occur in two possible locations in the TPB. Both occurrences can be related to the flow field of the reflow oven. Delta T of the TPB decreased when the conveyor speed (v) was reduced. A suitable conveyor speed (1.0 cm/s) was determined to maintain Delta T below 10 degrees C, which prevented the thermally critical package from overheating. Practical implications - The paper provies a methodology for designing a thermal profile for reflow soldering production. Originality/value - The findings provide fundamental guidelines to the thermal-coupling method at the board and package levels, very useful for accurate control of Delta T at the board and package levels, one of the major requirements in achieving a high degree of reliability for electronic assemblies.