Timing error calibration in time-interleaved ADC by sampling clock phase adjustment

被引：0

作者：

Liu, Zheng ^{[1
]}

Honda, Kazutaka ^{[1
]}

Furuta, Masanori ^{[2
]}

Kawahito, Shoji ^{[2
]}

机构：

[1] Shizuoka Univ, Grad Sch Elect Sci & Technol, Hamamatsu, Shizuoka 4328011, Japan

[2] Shizuoka Univ, Res Inst Elect, Hamamatsu, Shizuoka 4328011, Japan

来源：

2007 IEEE INSTRUMENTATION & MEASUREMENT TECHNOLOGY CONFERENCE, VOLS 1-5 | 2007年

关键词：

timing error; calibration; time-interleaved; ADC;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Timing error between sampling and holding(S/H) channels for Time-interleaved Analog-to-Digital Converts(TiADCs) is caused by clock skew and RC(sampling resistance and capacitance) mismatch. This paper presents the measurement results of a prototype chip basd on our previous work[10], in which we showed timing error due to clock skew and RC mismatch can be calibrated simultaneously by adjusting the clock phase. The results show that the residule timing error can be reduce to 1-ps.

引用

页码：1179 / +

页数：2

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