CMOS digital duty cycle correction circuit for multi-phase clock

被引：20

作者：

Jang, YC ^{[1
]}

Bae, SJ ^{[1
]}

Park, HJ ^{[1
]}

机构：

[1] Pohang Univ Sci & Technol, Dept EE, Pohang, South Korea

来源：

ELECTRONICS LETTERS | 2003年 / 39卷 / 19期

关键词：

Digital duty cycle correction circuit - Multiphase clock - Timing diagram;

D O I：

10.1049/el:20030908

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications with the multi-phase clock and the standby mode. Two integrators are used in the duty cycle detector to eliminate the effect of reference voltage variations. The output duty cycle is adjusted to 50 +/- 0.25% throughout the input duty cycle range from 20% to 80% at the frequency of 1.25 GHz. 0.18 mum CMOS technology is used in this work.

引用

页码：1383 / 1384

页数：2

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