Comparative Study of 6.5 kV 4H-SiC Discrete Packaged MOSFET, JBSFET, and Co-Pack (MOSFET and JBS Diode)

被引：1

作者：

Yun, Nick ^{[1
]}

Lynch, Justin ^{[1
]}

Morgan, Adam J. ^{[1
]}

Xing, Dang ^{[2
]}

Jin, Michael ^{[2
]}

Qianb, Jiashu ^{[2
]}

Kang, Minseok ^{[2
]}

Amarasinghe, Voshadhi ^{[3
]}

Ransom, John ^{[3
]}

Veliadis, Victor

Agarwal, Anant ^{[2
]}

Sung, Woongje ^{[1
]}

机构：

[1] Iinivers New York Polytechn Inst, Coll Nanoscale Sci & Engn, Albany, NY 12203 USA

[2] Ohio State Univ, Dept Elect & Comp Engn, Columbus, OH 43210 USA

[3] North Carolina State Univ, PowerAmer Inst, Raleigh, NC 27695 USA

来源：

2022 IEEE 34TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD) | 2022年

关键词：

Silicon Carbide; 4H-SiC; MOSFET; JBSFET; Co-Package; Medium Voltage; Double Pulse Test (DPT); Switching; Short Circuit Capability; Stress; Body Diode Degradation;

D O I：

10.1109/ISPSD49238.2022.9813639

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper reports the detailed comparison of packaged level, 6.5 kV rated 4H-SiC power MOSFET, MOSFET co-packaged with JBS diode (Co-Pack), and monolithically integrated 6.5 kV 4H-SiC MOSFET and JBS diode (JBSFET). JBSFET was designed to disable the PIN turn for reliability purposes and save the chip and process cost from the one-chip integration and single metal scheme. Static and dynamic electrical characteristics of stand-alone MOSFET, Co-Pack, and JBSFET are compared to signify the benefit of JBSFET in terms of performance, reliability, and economical point of view.

引用

页码：249 / 252

页数：4

共 9 条

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