Design and optimization of FinFETs for ultra-low-voltage analog applications

被引：93
作者：
Kranti, Abhinav
Armstrong, G. Alastair
机构：
[1] Northern Ireland Semiconductor Research Centre (NISRC), School of Electrical and Electronic Engineering, Queen's University Belfast
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2007年 / 54卷 / 12期
基金：
英国工程与自然科学研究理事会;
关键词：
capacitances; cutoff frequency; Early voltage; FinFETs; intrinsic voltage gain; source/drain extension (SDE) region engineering; transconductance-to-current ratio; ultra-low-voltage (ULV) analog design;
D O I：
10.1109/TED.2007.908596
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.
引用
收藏
页码：3308 / 3316
页数：9
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