A 32.5-GS/s Sampler With Time-Interleaved Track-and-Hold Amplifier in 65-nm CMOS

This paper presents a high-speed and low feed-through sampler with two-channel time-interleaved track-and-hold amplifiers (THAs). The THA is based on switched buffer with active inductors load such that wide bandwidth in track-mode and small-signal feed-through in hold-mode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor is also introduced to cancel clock feed-through in hold-mode. With two-channel accurate on-chip clock and its distribution network, double sampling rate is achieved due to the two-channel time-interleaved structure used. The chip was fabricated in 65-nm RF-CMOS process with core area of 0.07 mm(2) and power consumption of 211 mW. The measurements show that the S-parameters matched input and output up to 40 GHz with 19.3-GHz bandwidth in track-mode, the spurious-free-dynamic-range above 35 dB and total harmonic distortion below -30 dB up to 6 GHz when the sampling rate is 16.26 GS/s for one channel.