A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

被引:59
作者
Inti, Rajesh [1 ]
Yin, Wenjing [1 ]
Elshazly, Amr [1 ]
Sasidhar, Naga [1 ]
Hanumolu, Pavan Kumar [1 ]
机构
[1] Oregon State Univ, Dept Elect Engn & Comp Sci, Corvallis, OR 97331 USA
基金
美国国家科学基金会;
关键词
Digital CDR; reference-less frequency acquisition; data duty cycle error; linear delay cell; clock phase calibration; optimal sampling; power spectral density of random NRZ data; CLOCK; DESIGN; PHASE;
D O I
10.1109/JSSC.2011.2168872
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A reference-less highly digital half-rate clock and data recovery (CDR) circuit with improved tolerance to input duty cycle error is presented. Using a chain of frequency dividers, the proposed frequency detector produces a known sub-harmonic tone from the incoming random data. A digital frequency-locked loop uses the extracted tone, and drives the oscillator to any sub-rate of the input data frequency. The early/late outputs of a conventional half-rate bang-bang phase detector are used to determine the duty-cycle error in the incoming random data and adjust the oscillator clock phases to maximize receiver timing margins. Fabricated in 0.13 mu m CMOS technology, the prototype digital CDR operates without any errors from 0.5 Gb/s to 2.5 Gb/s. At 2 Gb/s, the prototype consumes 6.1 mW power from a 1.2 V supply. The proposed clock-phase calibration is capable of correcting upto +/- 20% of input data duty-cycle error.
引用
收藏
页码:3150 / 3162
页数:13
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