ESD Protection Diodes in Bulk Si Gate-All-Around Vertically Stacked Horizontal Nanowire Technology

被引：2

作者：

Chen, Shih-Hung ^{[1
]}

Hellings, Geert ^{[1
]}

Linten, Dimitri ^{[1
]}

Mertens, Hans ^{[1
]}

Mocuta, Anda ^{[1
]}

Horiguchi, Naoto ^{[1
]}

机构：

[1] IMEC, Dept Technol Solut & Enablement, B-3001 Leuven, Belgium

来源：

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2019年 / 19卷 / 01期

关键词：

Electrostatic discharge (ESD); ESD protection diodes; gate-all-around (GAA) nanowires; transmission line pulse (TLP); very fast TLP (vfTLP);

D O I：

10.1109/TDMR.2018.2886399

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For sub-5 nm bulk Si CMOS, a gate-all-around (GAA) nanowire (NW) device is a promising candidate. The new device architecture will have an impact on the transient performance of an electrostatic discharge protection diode. The 100 ns transmission line pulse (TLP) and 2 ns very fast TLP measurement results and TCAD simulations prove that the performance in bulk GAA NW-based diodes is maintained in comparison to bulk FinFET diodes.

引用

页码：112 / 119

页数：8