Improved LDMOS-SCR for high-voltage electrostatic discharge (ESD) protection applications

被引：6

作者：

Song, Wenqiang ^{[1
]}

Hou, Fei ^{[1
]}

Du, Feibo ^{[1
]}

Liu, Jizhi ^{[1
]}

Liu, Zhiwei ^{[1
]}

Liou, Juin J. ^{[1
,2
]}

机构：

[1] Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Chengdu 610054, Peoples R China

[2] Shenzhen Univ, Coll Elect & Informat Engn, Shenzhen, Peoples R China

来源：

ELECTRONICS LETTERS | 2020年 / 56卷 / 13期

关键词：

electrostatic discharge; thyristors; MIS devices; p-i-n diodes; improved LDMOS-SCR; high-voltage electrostatic discharge protection applications; ESD current discharges; high holding voltage; high failure current; HBM ESD stress; improved lateral double-diffused MOS silicon-controlled rectifier; surface gated PIN diode path; BCD process; size; 0; 18; mum; voltage; 5; V; 24; current; 10; 04; A; 15; kV; DUAL-DIRECTION SCR; HOLDING VOLTAGE;

D O I：

10.1049/el.2020.0748

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An improved lateral double-diffused MOS silicon-controlled rectifier (ILDMOS-SCR) for high-voltage electrostatic discharge (ESD) protection applications has been proposed and verified in a 0.18 mu m 5 V/24 V BCD process. The proposed improved lateral double-diffused MOS silicon-controlled rectifier (LDMOS-SCR) is constructed by adding a gated P-type/intrinsic/N-type (PIN) diode into a conventional LDMOS-SCR. With part of the ESD current discharges from the surface gated PIN diode path, the proposed ILDMOS-SCR achieves a high holding voltage of 30 V as well as a high failure current of 10.04 A, which is evaluated to pass 15 KV Human Body Model (HBM) ESD stress.

引用

页码：680 / 681

页数：2

共 50 条

[31] Performance and Reliability Co-design of LDMOS-SCR for Self-Protected High Voltage Applications On-Chip
Kranthi, Nagothu Karmel
Kumar, B. Sampath
Salman, Akram
Boselli, Gianluca
Shrivastava, Mayank
2019 31ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2019, : 407 - 410
[32] Novel robust high voltage ESD claws for LDMOS protection
Walker, A. J.
Ward, S. T.
Puchner, H.
2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL, 2007, : 596 - +
[33] TCAD methodology for design of SCR devices for electrostatic discharge (ESD) applications
Salcedo, Javier A.
Liou, Juin J.
Liu, Zhiwei
Vinson, James E.
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (04) : 822 - 832
[34] Design of a Gate Diode Triggered SCR for Dual-Direction High-Voltage ESD Protection
Liang, Hailian
Xu, Qiang
Zhu, Ling
Gu, Xiaofeng
Sun, Guipeng
Lin, Fen
Zhang, Sen
Xiao, Kui
Yu, Zhiguo
IEEE ELECTRON DEVICE LETTERS, 2019, 40 (02) : 163 - 166
[35] 多晶硅栅对LDMOS-SCR器件ESD防护性能的影响
黄龙
梁海莲
顾晓峰
董树荣
毕秀文
魏志芬
浙江大学学报(工学版), 2015, 49 (02) : 366 - 370
[36] Robust dual-direction SCR with low trigger voltage, tunable holding voltage for high-voltage ESD protection
Wang, Yang
Jin, Xiangliang
Yang, Liu
Jiang, Qi
Yuan, Huihui
MICROELECTRONICS RELIABILITY, 2015, 55 (3-4) : 520 - 526
[37] Physical Insights into the Low Current ESD Failure of LDMOS-SCR and Its Implication on Power Scalability
Kranthi, Nagothu Karmel
Kumar, B. Sampath
Salman, Akram
Boselli, Gianluca
Shrivastava, Mayank
2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2019,
[38] An SCR-Incorporated BJT Device for Robust ESD Protection With High Latchup Immunity in High-Voltage Technology
Huang, Chih-Yao
Chiu, Fu-Chien
Chen, Quo-Ker
Lai, Ming-Fang
Tseng, Jen-Chou
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2012, 12 (01) : 113 - 123
[39] ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC
Dai, Chia-Tsen
Ker, Ming-Dou
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (05) : 1996 - 2002
[40] Study on ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Applications
Dai, Chia-Tsen
Ker, Ming-Dou
2014 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2014,

← 1 2 3 4 5 →