Fault tolerant approaches targeting ultra low power communications system design

This paper presents a new approach to co-designing communication systems and their respective hardware architectures. We show that by taking into account the specific needs and assumptions of the algorithms running on hardware, the circuit specifications targeted by ASIC engineers can be relaxed. This in turn leads to optimal designs in both power consumption and robustness. A case-study of a complete WCDMA modem incorporating this approach shows a savings of 23% in embedded memory power consumption and a total of 13% power savings for the whole system.