Formation and Evaluation of Electroless-Plated Barrier Films for High-Aspect-Ratio Through-Si Vias

被引:6
作者
Miyake, Hiroshi [1 ]
Inoue, Fumihiro [1 ]
Yokoyama, Takumi [1 ]
Shimizu, Tomohiro [1 ]
Tanaka, Shukichi [2 ]
Terui, Toshifumi [2 ]
Shingubara, Shoso [1 ]
机构
[1] Kansai Univ, Grad Sch Sci & Engn, Osaka 5648680, Japan
[2] Kobe Adv Res Ctr, Natl Inst Informat & Commun Technol, Kobe, Hyogo 6512492, Japan
基金
日本学术振兴会;
关键词
SELF-ASSEMBLED-MONOLAYER; 3-DIMENSIONAL CHIP STACKING; BOTTOM-UP FILL; CU SEED LAYER; COPPER; DEPOSITION; FABRICATION; HOLES; ELECTRODEPOSITION; METAL;
D O I
10.1143/JJAP.50.05ED01
中图分类号
O59 [应用物理学];
学科分类号
摘要
The formation of a diffusion barrier layer in a through-Si via (TSV) has been studied with a combination of nanoparticle catalyst and electroless plating (ELP). We used Au-nanoparticles (Au-NPs) or Pd-nanoparticles (Pd-NPs) as catalysts for ELP of Ni- and Co-alloy barrier layers. We studied deposition of Ni-B and Co-B films in high-aspect-ratio (AR) TSV. Then, we succeeded in controlling the deposition profile of Ni- B in a high-AR TSV by the addition of bis(3-sulfopropyl)-disulfide (SPS). SPS turned out to be an inhibitor of electroless plating of Ni-B. On the other hand, the Co-B film was deposited conformally without additive. The electrical resistivity of Cu after annealing Cu/barrier stacked structure suggests that Co-B has better thermal stability than Ni-B. (C) 2011 The Japan Society of Applied Physics
引用
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页数:5
相关论文
共 20 条
[11]  
Koyanagi M., 2008, IEEE INT 3D SYST INT, P31
[12]   Electroless Ni-Mo-P diffusion barriers with Pd-activated self-assembled monolayer on SiO2 [J].
Liu, Dian-long ;
Yang, Zhi-gang ;
Zhang, Chi .
MATERIALS SCIENCE AND ENGINEERING B-ADVANCED FUNCTIONAL SOLID-STATE MATERIALS, 2010, 166 (01) :67-75
[13]   Changing Superfilling Mode for Copper Electrodeposition in Blind Holes from Differential Inhibition to Differential Acceleration [J].
Luehn, O. ;
Radisic, A. ;
Vereecken, P. M. ;
Van Hoof, C. ;
Ruythooren, W. ;
Celis, J. -P. .
ELECTROCHEMICAL AND SOLID STATE LETTERS, 2009, 12 (05) :D39-D41
[14]   Electroless deposited cobalt-tungsten-boron capping barrier metal on damascene copper interconnection [J].
Nakano, H ;
Itabashi, T ;
Akahoshi, H .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2005, 152 (03) :C163-C166
[15]   Influence of annealing conditions on the mechanical and microstructural behavior of electroplated Cu-TSV [J].
Okoro, Chukwudi ;
Vanstreels, Kris ;
Labie, Riet ;
Luhn, Ole ;
Vandevelde, Bart ;
Verlinden, Bert ;
Vandepitte, Dirk .
JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2010, 20 (04)
[16]   Fabrication of electroless NiReP barrier layer on SiO2 without sputtered seed layer [J].
Osaka, T ;
Takano, N ;
Kurokawa, T ;
Ueno, K .
ELECTROCHEMICAL AND SOLID STATE LETTERS, 2002, 5 (01) :C7-C10
[17]   Fabrication of Electroless CoWP/NiB Diffusion Barrier Layer on SiO2 for ULSI Devices [J].
Osaka, Tetsuya ;
Aramaki, Hitoshi ;
Yoshino, Masahiro ;
Ueno, Kazuyoshi ;
Matsuda, Itsuaki ;
Shacham-Diamand, Yosi .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2009, 156 (09) :H707-H710
[18]   Bottom-up fill of copper in deep submicrometer holes by electroless plating [J].
Shingubara, S ;
Wang, ZL ;
Yaegashi, O ;
Obata, R ;
Sakaue, H ;
Takahagi, T .
ELECTROCHEMICAL AND SOLID STATE LETTERS, 2004, 7 (06) :C78-C80
[19]   High-aspect-ratio copper via filling used for three-dimensional chip stacking [J].
Sun, JJ ;
Kondo, K ;
Okamura, T ;
Oh, SJ ;
Tomisaka, M ;
Yonemura, H ;
Hoshino, M ;
Takahashi, K .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2003, 150 (06) :G355-G358
[20]   Bottom-up fill for submicrometer copper via holes of ULSIs by electroless plating [J].
Wang, ZL ;
Yaegashi, O ;
Sakaue, H ;
Takahagi, T ;
Shingubara, S .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2004, 151 (12) :C781-C785