Intel's EUV resist development

被引：18

作者：

Cao, HD ^{[1
]}

Roberts, J ^{[1
]}

Dalin, J ^{[1
]}

Chandhok, M ^{[1
]}

Meagley, R ^{[1
]}

Panning, E ^{[1
]}

Shell, M ^{[1
]}

Rice, B ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2 | 2003年 / 5039卷

关键词：

extreme ultraviolet (EUV) lithography; photoresist; line width roughness (LWR); absorbance;

D O I：

10.1117/12.485095

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

The success of extreme ultraviolet (EUV) lithography depends upon developing resists that meet the patterning requirements for the technology node in which EUV is inserted. This paper presents Intel's patterning requirements and development strategies for EUV resists. Two of the primary problems for EUV resists are meeting the linewidth roughness (LWR) requirement, and reducing resist absorbance to obtain good sidewall profiles. Benchmarking data shows that none of the current EUV photoresists meet LWR targets. Modeling results for EUV resists show the impact of resist absorbance on sidewall angle and resolution.

引用

页码：484 / 491

页数：8