Advanced Arsenic Doped Epitaxial Growth for Source Drain Extension Formation in Scaled FinFET Devices

被引：0

作者：

Mochizuki, S. ^{[1
]}

Colombeau, B. ^{[2
]}

Yu, L. ^{[1
]}

Dube, A. ^{[2
]}

Choi, S. ^{[1
]}

Stolfi, M. ^{[2
]}

Bi, Z. ^{[1
]}

Chang, F. ^{[2
]}

Conti, R. A. ^{[1
]}

Liu, P. ^{[2
]}

Winstel, K. R. ^{[1
]}

Jagannathan, H. ^{[1
]}

Gossmann, H. -J. ^{[2
]}

Loubet, N. ^{[1
]}

Canaperi, D. F. ^{[1
]}

Guo, D. ^{[1
]}

Sharma, S. ^{[2
]}

Chu, S. ^{[2
]}

Boland, J. ^{[2
]}

Jin, Q. ^{[2
]}

Li, Z. ^{[2
]}

Lin, S. ^{[2
]}

Cogorno, M. ^{[2
]}

Chudzik, M. ^{[2
]}

Natarajan, S. ^{[2
]}

McHerron, D. C. ^{[1
]}

Haran, B. ^{[1
]}

机构：

[1] IBM Res, 257 Fuller Rd,Suite 3100, Albany, NY 12203 USA

[2] Appl Mat Inc, 974 E Arques Ave, Sunnyvale, CA 94085 USA

来源：

2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to the current state-of-the-art SDE formation in FinFET at l0nm logic ground rules. It is found that a Si:As layer based SDE provides a clear improvement in the short channel effect and a significant device performance increase. It is also shown that a careful co-optimization of the Si:As layer and Source/Drain (S/D) lateral recess is required to achieve the optimum device gain. This paves the way for the ultimate nSDE formation for current and next generation CMOS devices.

引用

页数：4