Statistical modeling of leakage currents through SiO2/high-κ dielectrics stacks for non-volatile memory applications

被引：17

作者：

Padovani, Andrea ^{[1
]}

Larcher, Luca ^{[2
]}

Verma, Sarves ^{[3
]}

Pavan, Paolo ^{[2
]}

Majhi, Prashant ^{[4
]}

Kapur, Pawan ^{[3
]}

Parat, Krishna ^{[4
]}

Bersuker, Gennadi ^{[5
]}

Saraswat, Krishna ^{[3
]}

机构：

[1] Univ Ferrara, Dipartimento Ingn, Via Saragat 1, I-44100 Ferrara, FE, Italy

[2] Univ Modena, DISMI, I-42100 Modena, Italy

[3] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

[4] Intel Corp, Santa Clara, CA USA

[5] SEMATECH, Austin, TX USA

来源：

2008 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 46TH ANNUAL | 2008年

关键词：

high-kappa; Flash memories; modeling; leakage current modeling; dielectrics;

D O I：

10.1109/RELPHY.2008.4558955

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-kappa dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-kappa's traps on leakage current distribution for Flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-kappa tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-kappa tunnel stacks and to improve technology-reliability issues related to Flash memory applications.

引用

页码：616 / +

页数：3

共 29 条

[1]

BERSUKER G, 2008, VLSI TECH S UNP

[2] A model for multistep trap-assisted tunneling in thin high-k dielectrics -: art. no. 044107 [J].

Blank, O ;

Reisinger, H ;

Stengl, R ;

Gutsche, M ;

Wiest, F ;

Capodieci, V ;

Schulze, J ;

Eisele, I .

JOURNAL OF APPLIED PHYSICS, 2005, 97 (04)

[3]

Buckley J., 2006, IEDM

[4] Modeling of tunnelling currents in Hf-based gate stacks as a function of temperature and extraction of material parameters [J].

Campera, Andrea ;

Iannaccone, Giuseppe ;

Crupi, Felice .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (01) :83-89

[5] Statistical model for random telegraph noise in Flash memories [J].

Compagnoni, Christian Monzio ;

Gustneroli, Riccardo ;

Spinelli, Alessandro S. ;

Lacaita, Andrea L. ;

Bonanomi, Mauro ;

Visconti, Angelo .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (01) :388-395

[6] NROM: A novel localized trapping, 2-bit nonvolatile memory cell [J].

Eitan, B ;

Pavan, P ;

Bloom, I ;

Aloni, E ;

Frommer, A ;

Finzi, D .

IEEE ELECTRON DEVICE LETTERS, 2000, 21 (11) :543-545

[7] VARIOT: A novel multilayer tunnel barrier concept, for low-voltage nonvolatile memory devices [J].

Govoreanu, B ;

Blomme, P ;

Rosmeulen, M ;

Van Houdt, J ;

De Meyer, K .

IEEE ELECTRON DEVICE LETTERS, 2003, 24 (02) :99-101

[8] A model for tunneling current in multi-layer tunnel dielectrics [J].

Govoreanu, B ;

Blomme, P ;

Rosmeulen, M ;

Van Houdt, J ;

De Meyer, K .

SOLID-STATE ELECTRONICS, 2003, 47 (06) :1045-1053

[9]

HAN JP, 2003, VLSI S, P161

[10] Spatial distributions of trapping centers in HfO2/SiO2 gate stack [J].

Heh, Dawei ;

Young, Chadwin D. ;

Brown, George A. ;

Hung, P. Y. ;

Diebold, Alain ;

Vogel, Eric M. ;

Bernstein, Joseph B. ;

Bersuker, Gennadi .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (06) :1338-1345

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