Two-dimensional analytical modeling of the surface potential and drain current of a double-gate vertical t-shaped tunnel field-effect transistor

被引:19
作者
Singh, Shailendra [1 ]
Raj, Balwinder [1 ]
机构
[1] Natl Inst Technol Jalandhar, Dept Elect & Commun Engn, Nanoelect Res Lab, Jalandhar 144011, Punjab, India
关键词
Analytical modeling; Double-gate vertical t-shaped TFET (DG V t-TFET); Band-two-band tunneling (B2BT); Poisson's equation; Subthreshold swing (SS); Parabolic approximation; Surface potential;
D O I
10.1007/s10825-020-01496-4
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present a two-dimensional (2-D) analytical modeling of the surface potential of a double-gate vertical t-shaped tunnel field-effect transistor (TFET), considering the inherit dual modulation effect in such devices. This effect explains the control of the surface potential by both bias voltages, which are used to calculate the tunneling depletion width at the source and drain junctions. A model of the tunneling current in the device is derived based on the surface-potential model. The parabolic approximation is used to solve the 2-D Poisson equation with appropriate boundary conditions. The dependence of the surface potential profile on different parameters is analyzed by varying the gate-source potential, drain-source potential, gate oxide dielectric constant, gate metal work function, and different materials used. Finally, expressions for the surface potential of the channel along with the tunneling current are obtained, accurately capturing their variation with the gate and drain biases. The proposed method is verified by the agreement between its analytical results and technology computer-aided design (TCAD) simulation results.
引用
收藏
页码:1154 / 1163
页数:10
相关论文
共 30 条
[1]  
[Anonymous], 2017, SENT US MAN
[2]  
[Anonymous], 2012, IEEE INT EL DEV M
[3]  
[Anonymous], 2015, International Technology Roadmap for Semiconductors 2015 edition, more Moore
[4]   Design and Analysis of Dual Source Vertical Tunnel Field Effect Transistor for High Performance [J].
Badgujjar, Soniya ;
Wadhwa, Girish ;
Singh, Shailendra ;
Raj, Balwinder .
TRANSACTIONS ON ELECTRICAL AND ELECTRONIC MATERIALS, 2020, 21 (01) :74-82
[5]   Surface Potential and Drain Current Analytical Model of Gate All Around Triple Metal TFET [J].
Bagga, Navjeet ;
Dasgupta, Sudeb .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (02) :606-613
[6]   Double-gate tunnel FET with high-κ gate dielectric [J].
Boucart, Kathy ;
Mihai Ionescu, Adrian .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) :1725-1733
[7]   Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor [J].
Chen, Shupeng ;
Liu, Hongxia ;
Wang, Shulong ;
Li, Wei ;
Wang, Xing ;
Zhao, Lu .
NANOSCALE RESEARCH LETTERS, 2018, 13
[8]   Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec [J].
Choi, Woo Young ;
Park, Byung-Gook ;
Lee, Jong Duk ;
Liu, Tsu-Jae King .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (08) :743-745
[9]   T-Shaped III-V Heterojunction Tunneling Field-Effect Transistor [J].
Dubey, Prabhat Kumar ;
Kaushik, Brajesh Kumar .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (08) :3120-3125
[10]   A 2-D Analytical Model for Double-Gate Tunnel FETs [J].
Gholizadeh, Mahdi ;
Hosseini, Seyed Ebrahim .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (05) :1494-1500