Design and Analysis of an Arithmetic and Logic Unit using Single Electron Transistor

被引:0
作者
Aarthy, M. [1 ]
Sridevi, Sriadibhatla [1 ]
机构
[1] Vellore Inst Technol, Dept Micro & Nano Elect, Vellore, Tamil Nadu, India
关键词
Single electron transistor; reversible logic gates; low power; speed; COMPACT ANALYTICAL-MODEL; SET MODEL; DEVICES;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The demand for low power dissipation and increasing speed elicits numerous research efforts in the field of nano CMOS technology. The Arithmetic Logic Unit is the core of any central processing unit. In this paper, we designed a 4-bit Arithmetic and Logic Unit (ALU) using Single Electron Transistor (SET). Single-electron transistor (SET) is a new type of switching nanodevice that uses controlled single-electron tunneling to amplify the current. The single-electron transistor ( SET) is highly scalable and possesses ultra-low power consumption when compared to conventional semiconductor devices. Reversible logic gates designed using SET are used for performing 4-bit arithmetic operations. We modelled symmetric single gate SET operating at room temperature using Verilog A code. The design is carried out in cadence simulation environment. The 4-bit SET based ALU design exhibits the power of 0.52 nW and delay of 350pS.
引用
收藏
页码:117 / 124
页数:8
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