An evaluation of the CMOS Technology Roadmap from the point of view of variability, interconnects, and power dissipation

被引：24

作者：

Boeuf, Frederic ^{[1
]}

Sellier, Manuel ^{[1
]}

Farcy, Alexis ^{[1
]}

Skotnicki, Thomas ^{[1
]}

机构：

[1] STMicroelectronics, F-38920 Crolles, France

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 06期

关键词：

CMOS integrated circuits; CMOS roadmaps; logic design; MOSFET logic devices; semiconductor logic devices; SRAM chips; variability;

D O I：

10.1109/TED.2008.921274

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, using the new generation of Model for Assessment of cmoS Technologies And Roadmaps software, we discuss the CMOS logic roadmap in terms of circuit performance, power dissipation, and variability, such as loaded ring-oscillator delay, as well as through 6T-SRAM functionality. It is shown that these criteria will have to be taken into account in addition to the traditional 17%-per-year delay improvement to construct a new industrially viable roadmap.

引用

页码：1433 / 1440

页数：8

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