Process development and bonding quality investigations of silicon layer stacking based on copper wafer bonding

被引：26

作者：

Chen, KN ^{[1
]}

Chang, SM ^{[1
]}

Fan, A ^{[1
]}

Tan, CS ^{[1
]}

Shen, LC ^{[1
]}

Reif, R ^{[1
]}

机构：

[1] MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA

来源：

APPLIED PHYSICS LETTERS | 2005年 / 87卷 / 03期

关键词：

D O I：

10.1063/1.1995943

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Process development of silicon layer stacking based on copper wafer bonding, grind-back, and etch-back was applied to demonstrate a strong four-layer-stack structure. Bonded copper layers in this structure became homogeneous layers and did not show original bonding interfaces. This process can be used in three-dimensional integrated circuit applications. Voids and total bonded area after each layer stacking were investigated for the bonding quality after each layer stacking. Large wafer bows from high residual stresses result in the structure failure at the stacking of a high number of layers. (c) 2005 American Institute of Physics.

引用

页数：3

共 16 条

[1] 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration [J].