Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm

被引:1
|
作者
Han, Yiding [1 ]
Chakraborty, Koushik [1 ]
Roy, Sanghamitra [1 ]
Kuntamukkala, Vilasita [1 ]
机构
[1] Utah State Univ, Dept Elect & Comp Engn, Logan, UT 84322 USA
关键词
Algorithms; Design; Parallel CAD; floorplanning; GPU;
D O I
10.1145/1970353.1970356
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this article, we propose a novel floorplanning algorithm for GPUs. Floorplanning is an inherently sequential algorithm, far from the typical programs suitable for Single-Instruction Multiple-Thread (SIMT)-style concurrency in a GPU. We propose a fundamentally different approach of exploring the floorplan solution space, where we evaluate concurrent moves on a given floorplan. We illustrate several performance optimization techniques for this algorithm in GPUs. To improve the solution quality, we present a comprehensive exploration of the design space, including various techniques to adapt the annealing approach in a GPU. Compared to the sequential algorithm, our techniques achieve 6-188X speedup for a range of MCNC and GSRC benchmarks, while delivering comparable or better solution quality.
引用
收藏
页数:21
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