Packet Transactions: High-Level Programming for Line-Rate Switches

被引:191
作者
Sivaraman, Anirudh [1 ]
Cheung, Alvin [2 ]
Budiu, Mihai [3 ]
Kim, Changhoon [4 ]
Alizadeh, Mohammad [1 ]
Balakrishnan, Hari [1 ]
Varghese, George [5 ]
McKeown, Nick [6 ]
Licking, Steve [4 ]
机构
[1] MIT CSAIL, Cambridge, MA 02139 USA
[2] Univ Washington, Seattle, WA 98195 USA
[3] VMWare Res, Palo Alto, CA USA
[4] Barefoot Networks, Palo Alto, CA USA
[5] Microsoft Res, Redmond, WA USA
[6] Stanford Univ, Stanford, CA 94305 USA
来源
PROCEEDINGS OF THE 2016 ACM CONFERENCE ON SPECIAL INTEREST GROUP ON DATA COMMUNICATION (SIGCOMM '16) | 2016年
基金
美国国家科学基金会;
关键词
Programmable switches; stateful data-plane algorithms;
D O I
10.1145/2934872.2934900
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Many algorithms for congestion control, scheduling, network measurement, active queue management, and traffic engineering require custom processing of packets in the data plane of a network switch. To run at line rate, these data-plane algorithms must be implemented in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built. This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chips. The key challenge is that many data-plane algorithms create and modify algorithmic state. To achieve line-rate programmability for stateful algorithms, we introduce the notion of a packet transaction: a sequential packet-processing code block that is atomic and isolated from other such code blocks. We have developed this idea in Domino, a C-like imperative language to express data-plane algorithms. We show with many examples that Domino provides a convenient way to express sophisticated data-plane algorithms, and show that these algorithms can be run at line rate with modest estimated chip-area overhead.
引用
收藏
页码:15 / 28
页数:14
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