On the Computation/Memory Trade-Off in Software Defined Radios

Since J. Mitola's seminal work in the 90's, Software Defined Radios (SDRs) have been a hot topic in wireless communication research. Though many notable achievements were reported in the field, the scarcity of computational power on general purpose CPUs has always been a limiting factor. If conveniently applied within an SDR context, classical concepts known in computer science as space/time trade-offs can prove helpful when trying to mitigate this problem. This paper presents a novel criterion to design signal-processing software in an SDR terminal that we call Memory Acceleration (MA). The key feature of MA is making extensive use of memory resources of the SDR platform in order to accelerate the most critical signal processing functions. MA provides substantial acceleration factors when applied to conventional SDRs without reducing their peculiar flexibility and appears particularly suited to the implementation of a fully-SW SDR on a general-purpose processor (GPP). As a case study for the application of MA, results about the implementation of the ETSI DVB-T [1] Viterbi decoder [2] are presented. In such a case, MA provides an acceleration factor of 10.4x with respect to a standard, purely-computational implementation while having no impact on error correction performance of the decoder and by making no use of any other typical performance enhancement technique (e.g. low level programming or parallel computation).