Parameter optimization tool for enhancing on-chip network performance

被引：0
|
作者：
Riihimäki, J [1 ]
Salminen, E [1 ]
Kuusilinna, K [1 ]
Hämäläinen, T [1 ]
机构：
[1] Tampere Univ Technol, Inst Digital & Comp Syst, FIN-33720 Tampere, Finland
来源：
2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present a tool to be used in the optimization of interconnection parameters in order to achieve optimal performance and implementation with minimal costs. The optimization tool uses an iterative algorithm to optimize the interconnection parameters, such as data width, priorities, and the time an agent can reserve the interconnection, to fulfill the given constraints. In the used test case, the required area decreased 50% while 85% of the original bandwidth was obtained. This was due to improved arbitration process.
引用
收藏
页码：61 / 64
页数：4
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