A Physical Model for Grain-Boundary-Induced Threshold Voltage Variation in Polysilicon Thin-Film Transistors

Grain boundaries (GBs) in the channel region of polysilicon thin-film transistors (poly-Si TFTs) lead to large variations in the performance of TFTs (delay and power). In this paper, we present a physical model to characterize the GB-induced transistor threshold voltage variations considering not only the number but also the position and orientation of each GB in 3-D space. The estimated threshold voltage variations show a good agreement with experimental data and simulations performed by a numerical 3-D drift-diffusion device simulator. Using the proposed model, the impact of GBs on TFTs for various grain sizes, device sizes, and source-drain voltages is discussed in detail. Specifically, when the grain size is comparable to the size of the device, we observed that threshold voltage (V-th) variations significantly increase, and V-th-distributions are non-Gaussian. Finally, using our model, we predict and demonstrate the GB-induced variations under different crystallization methods, such as sequential lateral solidification.