A Physical Model for Grain-Boundary-Induced Threshold Voltage Variation in Polysilicon Thin-Film Transistors

被引:22
作者
Ho, Chih-Hsiang [1 ]
Panagopoulos, Georgios [1 ]
Roy, Kaushik [1 ]
机构
[1] Purdue Univ, Dept Elect Engn, W Lafayette, IN 47907 USA
基金
美国国家科学基金会;
关键词
Grain boundary (GB); polysilicon (poly-Si); thin-film transistor (TFT); V-th variations; POLYCRYSTALLINE SILICON; CIRCUIT; ENHANCEMENT; SIMULATION; DEPENDENCE; STATES; TFTS; SIZE;
D O I
10.1109/TED.2012.2205387
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Grain boundaries (GBs) in the channel region of polysilicon thin-film transistors (poly-Si TFTs) lead to large variations in the performance of TFTs (delay and power). In this paper, we present a physical model to characterize the GB-induced transistor threshold voltage variations considering not only the number but also the position and orientation of each GB in 3-D space. The estimated threshold voltage variations show a good agreement with experimental data and simulations performed by a numerical 3-D drift-diffusion device simulator. Using the proposed model, the impact of GBs on TFTs for various grain sizes, device sizes, and source-drain voltages is discussed in detail. Specifically, when the grain size is comparable to the size of the device, we observed that threshold voltage (V-th) variations significantly increase, and V-th-distributions are non-Gaussian. Finally, using our model, we predict and demonstrate the GB-induced variations under different crystallization methods, such as sequential lateral solidification.
引用
收藏
页码:2396 / 2402
页数:7
相关论文
共 30 条
[1]  
[Anonymous], 2009, SENT DEV SIM
[2]  
[Anonymous], 1989, Advanced Engineering Electromagnetics
[3]   Flexible technologies and smart clothing for citizen medicine, home healthcare, and disease prevention [J].
Axisa, F ;
Schmitt, PM ;
Gehin, C ;
Delhomme, G ;
McAdams, E ;
Dittmar, A .
IEEE TRANSACTIONS ON INFORMATION TECHNOLOGY IN BIOMEDICINE, 2005, 9 (03) :325-336
[4]   A statistical model to predict the performance variation of polysilicon TFTs formed by grain-enhancement technology [J].
Cheng, CF ;
Jagar, S ;
Poon, MC ;
Kok, CW ;
Chan, MS .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (12) :2061-2068
[5]   Periodically lateral silicon grains fabricated by excimer laser irradiation with a-Si spacers for LTPS TFTs [J].
Cheng, Huang-Chung ;
Tsai, Chun-Chien ;
Lu, Jian-Hao ;
Chen, Hsu-Hsin ;
Chen, Bo-Ting ;
Chang, Ting-Kuo ;
Lin, Ching-Wei .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2007, 154 (01) :J5-J10
[6]  
Chih-Hsiang Ho, 2011, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011, P695, DOI 10.1109/ASPDAC.2011.5722276
[7]   GRAIN-BOUNDARY STATES AND THE CHARACTERISTICS OF LATERAL POLYSILICON DIODES [J].
DEGRAAFF, HC ;
HUYBERS, M ;
DEGROOT, JG .
SOLID-STATE ELECTRONICS, 1982, 25 (01) :67-71
[8]   Threshold voltage uniformity enhancement for low-temperature polysilicon thin-film transistors using tilt alignment technique [J].
Hsieh, Szu-I ;
Chen, Hung-Tse ;
Chen, Yu-g Chen ;
Chen, Chi-Lin ;
King, Ya-Chin .
ELECTROCHEMICAL AND SOLID STATE LETTERS, 2006, 9 (07) :H57-H60
[9]   Statistical study of subthreshold characteristics in polycrystalline silicon thin-film transistors [J].
Kitahara, Y ;
Takagi, S ;
Sano, N .
JOURNAL OF APPLIED PHYSICS, 2003, 94 (12) :7789-7795
[10]   Thin-film transistor and ultra-large scale integrated circuit: Competition or collaboration [J].
Kuo, Yue .
JAPANESE JOURNAL OF APPLIED PHYSICS, 2008, 47 (03) :1845-1852