Settling Time of Mesochronous Clock Re-timing Circuits in the Presence of Timing Jitter

It is well known that timing jitter can degrade the bit error rate (BER) of receivers that recover clock information from the input data. In this paper, we show that timing jitter can also result in an indefinite increase in the settling time of clock recovery circuits, particularly in low swing mesochronous systems. Mesochronous clock retiming circuits are used to recover a clock of the correct phase from a clock of the correct frequency. Such receivers are required for repeaterless on-chip interconnects and in off-chip interconnects that use a forwarded clock. We first show how timing jitter can result in large increase in the settling time of the clock recovery circuit. Next, we model the circuit as a Markov chain with absorbing states. Here, the mean time of absorption of the Markov chain, which represents the mean settling time of the circuit, is determined. The model is validated by confirming its predictions with behavioural simulations of the circuit. Using insights provided by the model, techniques for reducing the settling time are proposed and their efficacy is confirmed with circuit level simulations.