Carbon nanotube bumps for LSI interconnect

被引：0

作者：

Soga, Ikuo ^{[1
,2
]}

Kondo, Daiyu ^{[1
,2
]}

Yamaguchi, Yoshitaka ^{[1
,2
]}

Twai, Taisuke ^{[1
,2
]}

Mizukoshi, Masataka ^{[1
,2
]}

Awano, Yuji ^{[1
,2
]}

Yube, Kunio ^{[3
]}

Fujii, Takashi ^{[3
]}

机构：

[1] Fujitsu Labs Ltd, Nanotechnol Res Ctr, 10-1 Morinosato Wakamiya, Atsugi, Kanagawa 2430197, Japan

[2] Fujitsu Ltd, Atsugi, Kanagawa 2430197, Japan

[3] Mitsubishi Gas Chem Co Inc, Tokyo 1250051, Japan

来源：

58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS | 2008年

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We demonstrate, for the first time, carbon nanotube (CNT) flip chip bumps for LSI modules. The CNT bump is composed of a bundle of multi-walled CNTs. Resilient and flexible CNT bumps make flip chip LSI modules resistant to thermal stress. Furthermore, CNT bumps have a low electrical resistance and robustness over electromigration. In the experiment, the CNT bumps were used to connect a test evaluation group (TEG) chip and a host substrate, and their electrical resistance was evaluated. We found that the electrical contacts of CNT bumps with the chip and the substrate are important. For a good electrical contact, the CNT bumps were coated with gold and fixed to the chip and substrate. The resultant CNT bump with a diameter of 170 mu m and a height of 100 mu m exhibited a low resistance of 2.3 Omega. We then evaluated the flexibility of CNT bumps by pressing the TEG chip and measuring the displacement. The displacement between the TEG chip and host substrate was 10-20 % of the bump height, demonstrating an excellent flexibility.

引用

页码：1390 / +

页数：3

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