An architecture of accelerating real-time multimedia for networking applications

被引：0

作者：

Hsiao, Yi-Mao ^{[1
]}

Wang, Chao-Yuan ^{[1
]}

Huang, Kuo-Chang ^{[1
]}

Chu, Yuan-Sun ^{[1
]}

机构：

[1] Natl Chung Cheng Univ, Dept Elect Engn, SoC Lab, Chiayi 621, Taiwan

来源：

2007 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS, VOLS 1 AND 2 | 2007年

关键词：

multimedia; dual CPU; architecture; FPGA; network;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With the increasing of multimedia application, the network traffic have become heavy and increased the CPU loading. The main limitations for real-time multimedia networking are memory copies and interrupts. In this paper, a proposed system which have a dual CPU architecture will accelerate real-time multimedia transfer on the networking. An FPGA prototyping- Versatile is designed and implemented that has an ARM (hard core) and an Uni-RISC. Compared with the traditional single CPU system, the proposed dual CPU architecture shows 37.89% performing improvement on an FPGA prototyping.

引用

页码：284 / 287

页数：4

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