Design and Analysis of a New Load less 4T SRAM Cell in Deep Submicron CMOS Technologies

The goal of this paper is to reduce the power and area of the Static Random Access Memory (SRAM) array while maintaining the competitive performance. Here the various configuration of SRAM array is designed using both the six-transistor (6T) SRAM cell and a new loadless four-transistor (4T) SRAM cell in deep sublnicron (130nm, 90nm and 65nm) CMOS technologies. Then it is simulated using HSPICE to check for its functionality, Static Noise Margin (SNM), power dissipation, area occupancy and access time. Except the precharge circuits and the basic storage cells, remaining part of the circuitry is same for both 6T SRAM array and New Loadless 9T SRAM array. Compared to the conventional 6T SRAM array, the new loadless 41 SRAM array consumes less power with less area in deep submicron CMOS technologies. Also the SNM of the new loadless 4T SRAM cell is as good as that of the 6T SRAM cell for higher values of Cell Ratio (CR).