Physical Level Design of Floating Point Multiplier using Vedic Mathematics

被引：0

作者：

Srinivasan, S., V ^{[1
]}

Rajak, Abdul A. R. ^{[1
]}

机构：

[1] Birla Inst Technol & Sci, Elect & Elect, Pilani, Dubai, U Arab Emirates

来源：

2015 INTERNATIONAL CONFERENCE ON EMERGING RESEARCH IN ELECTRONICS, COMPUTER SCIENCE AND TECHNOLOGY (ICERECT) | 2015年

关键词：

VLSI; nanotechnology; mathematics; binary sequences; computational efficiency;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The objective of the paper is to design a physical level chip for floating point multiplication using the concepts from Vedic Mathematics with VLSI 90nm technology. Vedic Mathematics has been a successful methodology in computing various basic calculations by faster means. But, its inefficiency to compute decimal calculations and controversy with speed, timing and power parameters in the digital chip has been a major drawback. In this paper, a floating point multiplier is constructed, extending an idea from whole number multiplication to decimal multiplication. The physical level design of the chip has been obtained using the tool called IC Compiler from Synopsys, Inc.

引用

页码：468 / 471

页数：4

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