Simulation based cause and effect analysis of cycle time distribution in semiconductor backend

被引：0

作者：

Sivakumar, AI ^{[1
]}

机构：

[1] Nanyang Technol Univ, Gint Inst Mfg Technol, Singapore 638075, Singapore

来源：

PROCEEDINGS OF THE 2000 WINTER SIMULATION CONFERENCE, VOLS 1 AND 2 | 2000年

关键词：

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

We analyzed the effect of a number of controllable input parameters on cycle time distribution and other output variables in a complex semiconductor backend manufacturing system, using a data driven, discrete event simulation model. A validated model was used as the base case and the effects were quantified against the base model to analyze the relative merits and sensitivity of each of these input variables. Input variables that are analyzed include lot release controls, heuristic scheduling rules, machine up time, setup time, material handling time, product flow, and lot size. We have used actual data from a major semiconductor back-end site for our analysis and showed the impact of lot release scheduling on cycle time distribution.

引用

页码：1464 / 1471

页数：8

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