Gate-all-around twin silicon nanowire SONOS memory

被引:26
作者
Suk, Sung Dae [1 ]
Yeo, Kyoung Hwan [1 ]
Cho, Keun Hwi [1 ]
Li, Ming [1 ]
Yeoh, Yun young [1 ]
Hong, Ki-Ha [4 ]
Kim, Sung-Han [3 ]
Koh, Young-Ho [2 ]
Jung, Sunggon [2 ]
Jang, WonJun [2 ]
Kim, Dong-Won [1 ]
Park, Donggun [1 ]
Ryu, Byung-Il [1 ]
机构
[1] Samsung Elect Co, Device Res Team, San 24, Yongin 449711, Kyoungi Do, South Korea
[2] Samsung Elect Co, PD Team, Yongin 449711, Kyoungi Do, South Korea
[3] Samsung Elect Co, Team MTT2, Yongin 449711, Kyoungi Do, South Korea
[4] SAIT, Yongin 449711, Kyoungi Do, South Korea
来源
2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年
关键词
D O I
10.1109/VLSIT.2007.4339760
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We have developed gate-all-around (GAA) SONOS with ultra thin twin silicon nanowires for the first time. By using channel hot electron injection (CHEI) and hot hole injection (HHI) mechanisms, program speed of 1 mu s at V-d=2 V, V-g =6 V and erase speed of 1 ms at V-d=4.5 V, V-g=-6 V are achieved with 2 similar to 3 nm nanowire and 30 nm gate. Nanowire size below 10 nm dependencies on V, shift (AV,) and the program/erase (P/E) characteristics are investigated. As nanowire diameter (d(nw)) decreases, faster program speed and larger Delta V-th are observed.
引用
收藏
页码:142 / +
页数:2
相关论文
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