Computation of AB2 multiplication in GF(2m) using low-complexity systolic architecture

An AB 2 operation is known as an efficient basic operation for public key cryptosystems over GF(2(m)), and various systolic arrays for performing AB(2) operations have already been proposed using a standard basis representation. However, these circuits have certain shortcomings for cryptographic application due to their high circuit complexity and long latency. Therefore, further research on an efficient AB(2) multiplication circuit is still needed. Accordingly, the authors present a new AB(2) algorithm and its systolic realisations in GF(2(m)). First, a new algorithm is proposed based on the MSB-first scheme using a standard basis representation. Thereafter, bitparallel and bit-serial systolic power multipliers are derived that exhibit a lower hardware complexity and smaller latency than conventional approaches. In addition, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied as a basic architecture for computing an inverse/ division operation and in crypto-processor chip design.