Booth folding encoding for high performance squarer circuits

被引：35

作者：

Strollo, AGM ^{[1
]}

De Caro, D ^{[1
]}

机构：

[1] Univ Naples Federico II, Dept Elect & Telecommun Engn, I-80125 Naples, Italy

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2003年 / 50卷 / 05期

关键词：

CMOS digital integrated circuits; digital integrated circuits; digital arithmetic; digital signal processors; fixed-point arithmetic; signal processing;

D O I：

10.1109/TCSII.2003.810574

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Combined Booth encoding and Folding technique is proposed to design squarer circuits using either carry-save or Wallace Tree addition techniques. Booth-Folded technique is compared with previous state of the art squarer architecture, showing that a remarkable improvement in Timing, Power and Area performances can be gained both for carry-save and Wallace Tree cases. Experimental results, that use built-in-self-test for measuring on chip squarers performances, are presented. The measurements confirm the advantages of Booth-Folded architecture.

引用

页码：250 / 254

页数：5

共 15 条

[1]

ARDEKANI JF, 1993, IEEE T VLSI SYST, V1, P120

[2]

Bickerstaff K. A. C., 1993, Proceedings. International Conference on Application-Specific Array Processors (Cat. No.93TH0572-8), P478, DOI 10.1109/ASAP.1993.397168

[3] Parallel squarer using Booth-folding technique [J].

De Caro, D ;

Strollo, AGM .

ELECTRONICS LETTERS, 2001, 37 (06) :346-347

[4] A fast parallel multiplier-accumulator using the modified Booth algorithm [J].

Elguibaly, F .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (09) :902-908

[5] A 54 X 54-B REGULARLY STRUCTURED TREE MULTIPLIER [J].

GOTO, G ;

SATO, T ;

NAKAJIMA, M ;

SUKEMURA, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (09) :1229-1236

[6] A 4.1-ns compact 54 x 54-b multiplier utilizing sign-select booth encoders [J].

Goto, G ;

Inoue, A ;

Ohe, R ;

Kashiwakura, S ;

Mitarai, S ;

Tsuru, T ;

Izawa, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (11) :1676-1682

[7] An Integrated Circuit Design for Pruned Tree-Search Vector Quantization Encoding with an Off-Chip Controller [J].

Jain, Rajeev ;

Madisetti, Avanindra ;

Baker, Richard L. .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 1992, 2 (02) :147-158

[8] VLSI implementation of 350MHz 0.35μm 8 bit merged squarer [J].

Kolagotla, RK ;

Griesbach, WR ;

Srinivas, HR .

ELECTRONICS LETTERS, 1998, 34 (01) :47-48

[9]

Pihl J, 1996, PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, P109, DOI 10.1109/MWSCAS.1996.594049

[10]

Proakis J.G., 1995, DIGITAL COMMUNICATIO

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