Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory

被引：0
作者：
Ikehashi, T [1 ]
Imamiya, K
Sakui, K
机构：
[1] Toshiba Corp Semicond Co, Memory Div, Memory LSI Res & Dev Ctr, Adv Memory Design Grp, Yokohama, Kanagawa 2478585, Japan
[2] Toshiba Corp Semicond Co, Memory Div, Memory LSI Res & Dev Ctr, Adv Memory Device Grp, Yokohama, Kanagawa 2358522, Japan
来源：
IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING | 2000年 / 23卷 / 04期
关键词：
contact hole diffusion; device simulation; drain spacing; ESD; HBM; lateral NPN bipolar protection; MM; nonsilicided junction; STI;
D O I：
10.1109/6104.895068
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n(-) junction with n(+) being implanted from contact holes, We have confirmed by measurements that the protection has sufficient robustness.
引用
收藏
页码：246 / 254
页数：9
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