The Opportunity Cost of Low Power Design: A Case Study in Circuit Tuning

被引：0

作者：

Ziegler, Matthew M. ^{[1
]}

Zyuban, Victor V. ^{[1
]}

Gristede, George D. ^{[1
]}

Vratonjic, Milena

Friedrich, Joshua

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

ISLPED 09 | 2009年

关键词：

Low Power Design; Circuit Tuning; Productivity;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The time-to-market pressures combined with the immense power reduction design space of VLSI design call for an evaluation of power savings opportunities prior to the investment in design effort. This paper presents an estimation methodology for predicting the power savings of circuit tuning for an industrial chip design project. A comparison between the estimated and actual power savings realized through tuning over 100 macros on the chip validates the accuracy of this estimation methodology.

引用

页码：133 / 138

页数：6

共 5 条

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[3] CPAM: A common power analysis methodology for high-performance VLSI design
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Chen, HH
Walker, SG
Venuto, J
Bucelot, TJ
[J]. ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2000, : 303 - 306
[4] Northrop GA, 2001, DES AUT CON, P426, DOI 10.1109/DAC.2001.935547
[5] VISWESWARIAH C, 1999, P INT C COMP AID DES, P244

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