On-chip interconnection networks of the trips chip

The trips chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170million-transistor custom asic chip, these nocs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. Our experience shows that nocs are area-and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.