On-chip interconnection networks of the trips chip

被引：64

作者：

Gratz, Paul ^{[1
]}

Kim, Changkyu

Sankaralingam, Karthikeyan

Hanson, Heather

Shivakumar, Premkishore

Keckler, Stephen W.

Burger, Doug

机构：

[1] Univ Texas, Dept Elect & Comp Engn, Austin, TX 78712 USA

[2] Univ Wisconsin, Madison, WI USA

来源：

IEEE MICRO | 2007年 / 27卷 / 05期

关键词：

Communication; Distributed architectures; Distributed processing; Interconnection networks; Multicore architectures; Networking; On-chip interconnection networks; Packet switching; Packet-switching networks;

D O I：

10.1109/MM.2007.4378782

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The trips chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170million-transistor custom asic chip, these nocs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. Our experience shows that nocs are area-and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.

引用

页码：41 / 50

页数：10

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