Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

被引：8
作者：
Shikha, U. S. [1 ]
James, Rekha K. [1 ]
Jacob, Jobymol [2 ]
Pradeep, Anju [1 ]
机构：
[1] Cochin Univ Sci & Technol, Sch Engn, Div Elect, Kochi, India
[2] Coll Engn Poonjar, Dept Elect Engn, Kottayam, Kerala, India
来源：
SILICON | 2022年 / 14卷 / 11期
关键词：
Negative capacitance; Tunnel field effect transistors; Drain current modeling; Double gate structure; Heterojunction; Tangent line approximation; TUNNEL FET;
D O I：
10.1007/s12633-021-01382-z
中图分类号：
O64 [物理化学（理论化学）、化学物理学];
学科分类号：
070304 ; 081704 ;
摘要：
The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (A(v)), which is an important parameter in NC devices is also analyzed.
引用
收藏
页码：6157 / 6167
页数：11
相关论文
共 25 条
  • [1] Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping
    Ahish, Shylendra
    Sharma, Dheeraj
    Kumar, Yernad Balachandra Nithin
    Vasantha, Moodabettu Harishchandra
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (01) : 288 - 295
  • [2] Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance
    Alper, C.
    De Michielis, L.
    Dagtekin, N.
    Lattanzio, L.
    Bouvet, D.
    Ionescu, A. M.
    [J]. SOLID-STATE ELECTRONICS, 2013, 84 : 205 - 210
  • [3] Carrillo-Nuñez H, 2014, PROC EUR S-STATE DEV, P118, DOI 10.1109/ESSDERC.2014.6948772
  • [4] Optimization of double metal-gate InAs/Si heterojunction nanowire TFET
    Choi, Yejoo
    Hong, Yuri
    Ko, Eunah
    Shin, Changhwan
    [J]. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 35 (07)
  • [5] A low subthreshold swing tunneling field effect transistor for next generation low power CMOS applications
    Chowdhury, Nadim
    Ahmed, Imtiaz
    Fakhrul, Takian
    Alam, M. K.
    Khosru, Quazi D. M.
    [J]. PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES, 2015, 74 : 251 - 257
  • [6] A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance
    Dash, S.
    Mishra, G. P.
    [J]. ADVANCES IN NATURAL SCIENCES-NANOSCIENCE AND NANOTECHNOLOGY, 2015, 6 (03)
  • [7] An Accurate Analytical Current Model of Double-gate Heterojunction Tunneling FET
    Guan, Yunhe
    Li, Zunchao
    Zhang, Wenhao
    Zhang, Yefei
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (03) : 938 - 944
  • [8] Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)
    Hu, Vita Pi-Ho
    Lin, Hung-Han
    Lin, Yen-Kai
    Hu, Chenming
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (06) : 2593 - 2599
  • [9] Investigation of Negative Capacitance Gate-all-Around Tunnel FETs Combining Numerical Simulation and Analytical Modeling
    Jiang, Chunsheng
    Liang, Renrong
    Xu, Jun
    [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2017, 16 (01) : 58 - 67
  • [10] ZENER TUNNELING IN SEMICONDUCTORS
    KANE, EO
    [J]. JOURNAL OF PHYSICS AND CHEMISTRY OF SOLIDS, 1959, 12 (02) : 181 - 188
123