A multi-channel architecture for high-performance NAND flash-based storage system

被引：107

作者：

Kang, Jeong-Uk ^{[1
]}

Kim, Jin-Soo ^{[1
]}

Park, Chanik ^{[1
]}

Park, Hyoungjun ^{[1
]}

Lee, Joonwon ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Div Comp Sci, Taejon 305701, South Korea

来源：

JOURNAL OF SYSTEMS ARCHITECTURE | 2007年 / 53卷 / 09期

关键词：

NAND flash memory; Storage system; I/O parallelism;

D O I：

10.1016/j.sysarc.2007.01.010

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Many mobile devices demand a large-capacity and high-performance storage system in order to store, retrieve, and process large multimedia data quickly. In this paper, we present a high-performance NAND flash-based storage system based on a multi-channel architecture. The proposed system consists of multiple independent channels, where each channel has multiple NAND flash memory chips. On this hardware, we investigate three optimization techniques to exploit I/O parallelism: striping, interleaving, and pipelining. By combining all the optimization techniques carefully, our system has shown 3.6 times higher overall performance compared to the conventional single-channel architecture. (c) 2007 Elsevier B.V. All rights reserved.

引用

页码：644 / 658

页数：15

共 14 条

[1]

ATWOOD G, 1997, INTEL STRATA FLASH M

[2]

Ban Amir, 1995, United States Patent, Patent No. [5,404,485, 5404485]

[3] An adaptive striping architecture for flash memory storage systems of embedded systems [J].

Chang, LP ;

Kuo, TW .

EIGHTH IEEE REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM, PROCEEDINGS, 2002, :187-196

[4]

Chiang ML, 1999, SOFTWARE PRACT EXPER, V29, P267, DOI 10.1002/(SICI)1097-024X(199903)29:3<267::AID-SPE233>3.0.CO

[5]

2-T

[6]

Douglis F., 1994, Proceedings of the First USENIX Symposium on Operating Systems Design and Implementation (OSDI), P25

[7]

KAWAGUCHI A, 1995, PROCEEDINGS OF THE 1995 USENIX TECHNICAL CONFERENCE, P155

[8]

Kim J, 2002, IEEE T CONSUM ELECTR, V48, P366

[9] A new NAND-type flash memory package with smart buffer system for spatial and temporal localities [J].

Lee, JH ;

Park, GH ;

Kim, SD .

JOURNAL OF SYSTEMS ARCHITECTURE, 2005, 51 (02) :111-123

[10] Cost-efficient memory architecture design of NAND flash memory embedded systems [J].

Park, C ;

Seo, J ;

Seo, DY ;

Kim, S ;

Kim, B .

21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, :474-480

← 1 2 →