Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology

被引：27

作者：

Wu, Yi-Ting ^{[1
]}

Ding, Fei ^{[2
]}

Connelly, Daniel ^{[2
]}

Zheng, Peng ^{[2
]}

Chiang, Meng-Hsueh ^{[1
]}

Chen, Jone F. ^{[1
]}

Liu, Tsu-Jae King ^{[2
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Inst Microelect, Tainan 701, Taiwan

[2] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2017年 / 64卷 / 10期

关键词：

FinFET; input and output (I/O); lateral double-diffused MOSFET (LDMOS); reduced surface field (RESURF); system-on-chip (SoC); DEVICE;

D O I：

10.1109/TED.2017.2736442

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A hybrid fin/planar lateral double-diffused MOSFET (LDMOS) design (hybrid FET) is proposed for the high-voltage input-output devices in a FinFET-based system-on-chip (SoC) technology. 3-D technology computer-aided design simulations show that a planar drift region and a planar drain region are advantageous for higher breakdown voltage (BV) to specific on-state resistance (R-on_sp) ratio (BV2/R-on_sp). By slightly extending the planar portion of the semiconductor active region into the gated channel region, the theoretical limit of BV2/R-on_sp for LDMOS can be surpassed. Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology.

引用

页码：4193 / 4199

页数：7

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