Vertically integrated silicon-germanium nanowire field-effect transistor

被引:23
作者
Rosaz, G. [1 ,2 ]
Salem, B. [1 ]
Pauc, N. [2 ]
Potie, A. [1 ]
Gentile, P. [2 ]
Baron, T. [1 ]
机构
[1] CEA Grenoble, LTM UMR CNRS UJF 5129, F-38054 Grenoble, France
[2] CEA Grenoble, INAC SP2M SiNaPS, F-38054 Grenoble, France
关键词
D O I
10.1063/1.3660244
中图分类号
O59 [应用物理学];
学科分类号
摘要
We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9V, an I-ON/I-OFF ratio of 10(4). The subthreshold slope was estimated to be around 0.9V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps D-it similar to 1.2 x 10(13) cm(-2) eV(-1). Comparisons are made with both vertical Si and horizontal SiGe FETs performances. (C) 2011 American Institute of Physics. [doi:10.1063/1.3660244]
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页数:3
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