High electron mobility transistors fabricated by nanoimprint lithography

被引:11
作者
Chen, Y [1 ]
Macintyre, DS [1 ]
Boyd, E [1 ]
Moran, D [1 ]
Thayne, I [1 ]
Thoms, S [1 ]
机构
[1] Univ Glasgow, Nanoelect Res Ctr, Dept Elect & Elect Engn, Glasgow G12 8LT, Lanark, Scotland
关键词
nanoimprint lithography; pHEMT; T-gates;
D O I
10.1016/S0167-9317(03)00183-7
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
High frequency low noise III-V transistors commonly have T-shaped gates since they provide a combination of short gate length and low gate resistance. This paper describes the fabrication of working pHEMT transistors with 120-nm T-shaped gates using a bi-layer nanoimprint lithography process. The main thrust of the work has been to develop a nanoimprinted T-gate process for the fabrication of pHEMTs. The fabrication of silicon stamping tools plays a vital part in transistor fabrication by this technique and the bi-layer enables removal of the residual resist without dry etch damage to the substrate. The paper describes the measures taken to achieve reliable uniform pattern transfer by nanoimprint lithography and the subsequent post imprint fabrication steps used to realise working transistors. The results of device characterisation are presented. (C) 2003 Elsevier Science B.V. All rights reserved.
引用
收藏
页码:189 / 195
页数:7
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