FLUX-1 RSFQ microprocessor: Physical design and test results

被引：43
作者：
Bunyk, P [1 ]
Leung, M
Spargo, J
Dorojevets, M
机构：
[1] TRW Space & Elect, Redondo Beach, CA 90278 USA
[2] SUNY Stony Brook, ECE Dept, Stony Brook, NY 11794 USA
来源：
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY | 2003年 / 13卷 / 02期
关键词：
D O I：
10.1109/TASC.2003.813890
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The Flux-1 chip is an RSFQ implementation of a small general-purpose processing engine with target clock frequency of 20 GHz and over 5000 gates (over 60K Josephson junctions) connected in an irregular pattern. The scale of this design task forced us to re-think conventional RSFQ design methodology and implement new approaches suitable for digital systems of this level of complexity and beyond. This paper presents lessons learned from the Flux-1 effort, mostly concentrating on chip physical design. Here we discuss or approach to the circuit design and verification of individual gates, gate interconnect using passive transmission lines and use of CAD tools for design automation and verification. A companion paper describes Flux-1 architecture.
引用
收藏
页码：433 / 436
页数：4
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