Integrated Advanced Hotspot Analysis Techniques in the Post-OPC Verification Flow

Improvements in compact lithography models and compute resources have allowed EDA suppliers to keep up with the accuracy and turnaround time (TAT) requirements for each new technology node. Compact lithography models are derived from the Hopkins method to calculate the image at the wafer. They consist of the pre-calculated optical kernel set that includes properties of projection and source optics as well as resist effects. The image at the wafer is formed by the convolution of optical kernel set with the mask transmission. The compact model is used for optical proximity correction (OPC) and lithography rule checking (LRC) due to its excellent turnaround time in full chip applications. Leading edge technology nodes, however, are inherently more sensitive to process variation and typically contain more low contrast areas, sometimes resulting in marginal hotspots. In these localized areas, it is desirable to have access to more predictive first principle lithography simulation. The Abbe method for lithography simulation includes full 3D resist models that solves from first principles the reaction/diffusion equation of the post exposure bake to provide the highest accuracy. These rigorous models have the ability to provide added insight into 3D developed profile in resist at the wafer level to assist in the application of OPC and disposition of hotspots found by LRC using compact models. This paper will explore the benefits of a tightly integrated rigorous lithography simulation during LRC hotspot detection step of the post OPC flow. Multiple user flows will be addressed along with methods for automating the flows to maximize the imaging predictability where needed while keeping the impact to turn around time to a minimum.