Design and Implementation of Optimal Soft-Programmable Logic Controller on Multicore Processor

被引:0
作者
Vasu, P. [1 ]
Chouhan, Harish [2 ]
Naik, Nitin [2 ]
机构
[1] PESIT BSC, Dept ECE, Bangalore, Karnataka, India
[2] MosChip Semicond Technol Ltd, Bangalore, Karnataka, India
来源
2017 INTERNATIONAL CONFERENCE ON MICROELECTRONIC DEVICES, CIRCUITS AND SYSTEMS (ICMDCS) | 2017年
关键词
ladder logic; multicore PLC; scantime; soft-PLC;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In the present industrial world, Programmable Logic Controllers (PLCs) are playing a vital role. A Programmable Logic Controller is a solid state user programmable control system with functions to control logic, sequencing, timing, arithmetic data manipulation and counting capabilities. As the applications are becoming more and more complex, the single-core PLCs are unable to meet the high speed execution requirements, so there is a need for high performance PLCs. Scan time is one of the important parameter which determines the performance of PLC. This paper presents an Optimal Software PLC (Soft-PLC) developed using python programming language which runs on multicore processor. The key feature of this Soft-PLC is the identification and parallel execution of independent rungs of ladder logic on multiple core. Our Soft-PLC provides high speed execution and low scan time compared to PLCs which run on single core processor.
引用
收藏
页数:4
相关论文
共 5 条
[1]  
Bolton W., 2009, PROGRAMMABLE LOGIC C, V5
[2]  
Bryan L.A., 1997, Programmable Controllers: Theory and Implementation
[3]  
Canedo A, 2012, DES AUT TEST EUROPE, P554
[4]   High Communication Throughput and Low Scan Cycle Time with Multi/Many-Core Programmable Logic Controllers [J].
Canedo, Arquimedes ;
Ludwig, Hartmut ;
Al Faruque, Mohammad Abdullah .
IEEE EMBEDDED SYSTEMS LETTERS, 2014, 6 (02) :21-24
[5]   A compiler for Ladder diagram to multi-core dataflow architecture [J].
Guo, Jiarong ;
Ran, Feng ;
Bi, Zhuo ;
Xu, Meihua .
MATERIAL SCIENCE AND ENGINEERING TECHNOLOGY, 2012, 462 :368-+