Hybrid DRAM/PRAM-based Main Memory for Single-Chip CPU/GPU

被引:0
|
作者
Kim, Dongki [1 ]
Lee, Sungkwang [1 ]
Chung, Jaewoong [2 ]
Kim, Dae Hyun [2 ]
Woo, Dong Hyuk [2 ]
Yoo, Sungjoo [1 ]
Lee, Sunggu [1 ]
机构
[1] POSTECH, Dept Elect Engn, Pohang, South Korea
[2] Intel Labs, Intel Crop, Pohang, South Korea
关键词
Main memory subsystem; single-chip CPU/GPU; phase-change RAM;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Single-chip CPU/GPU architecture is being adopted in high-end (embedded) systems, e. g., smartphones and tablet PCs. Main memory subsystem is expected to consist of hybrid DRAM and phase-change RAM (PRAM) due to the difficulties in DRAM scaling. In this work, we address the performance optimization of the hybrid DRAM/PRAM main memory for single chip CPU/GPU. Based on the tight requirements of low latency from CPU and the relative tolerance to long latency from GPU, DRAM is first allocated to CPU while PRAM with longer write latency is allocated to GPU. Then, in order to improve the write performance of GPU traffic, we propose (1) an in-DRAM write buffer to accommodate GPU write traffics, (2) dynamic hot data management to improve the efficiency of write buffer, (3) runtime-adaptive adjustment of write buffer size to meet the given CPU performance bound, and (4) CPU-aware DRAM access scheduling to give low latency to CPU traffics. The experiments show that the proposed method gives 1.02 similar to 44.2 times performance improvement in GPU performance with modest (negligible) CPU performance overhead (when compute-intensive CPU programs run).
引用
收藏
页码:888 / 896
页数:9
相关论文
共 50 条
  • [1] Power Management of Hybrid DRAM/PRAM-Based Main Memory
    Park, Hyunsun
    Yoo, Sungjoo
    Lee, Sunggu
    PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 59 - 64
  • [2] A Space Effective DRAM Adapter for PRAM-based Main Memory System
    Lee, Do-Heon
    Yoon, Su-Kyoung
    Kim, Jung-Geun
    Kim, Cheong-Gil
    Kim, Shin-Dug
    2013 INTERNATIONAL CONFERENCE ON IT CONVERGENCE AND SECURITY (ICITCS), 2013,
  • [3] PDRAM: A Hybrid PRAM and DRAM Main Memory System
    Dhiman, Gaurav
    Ayoub, Raid
    Rosing, Tajana
    DAC: 2009 46TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2009, : 664 - 669
  • [4] A dynamic adaptive converter and management for PRAM-based main memory
    Choi, In-Sung
    Jang, Sung-In
    Oh, Chang-Hoon
    Weems, Charles C.
    Kim, Shin-Dug
    MICROPROCESSORS AND MICROSYSTEMS, 2013, 37 (6-7) : 554 - 561
  • [5] Power-Aware Variable Partitioning for DSPs with Hybrid PRAM and DRAM Main Memory
    Liu, Tiantian
    Zhao, Yingchao
    Xue, Chun Jason
    Li, Minming
    PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 405 - 410
  • [6] Power-Aware Variable Partitioning for DSPs With Hybrid PRAM and DRAM Main Memory
    Liu, Tiantian
    Zhao, Yingchao
    Xue, Chun Jason
    Li, Minming
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2013, 61 (14) : 3509 - 3520
  • [7] DH-LRU: Dynamic Hybrid LRU Caching Scheme for PRAM/DRAM Hybrid Main Memory
    Ren, Yongjian
    Xie, Hongtianchen
    Jia, Gangyong
    Zhang, Jilin
    Yin, Yuyu
    Wan, Jian
    INTERNATIONAL JOURNAL OF GRID AND DISTRIBUTED COMPUTING, 2016, 9 (11): : 81 - 94
  • [8] Memory organization of a single-chip video signal processing system with embedded DRAM
    Hilgenstock, J
    Herrmann, K
    Pirsch, P
    NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, : 42 - 45
  • [9] Multiobjective Evolution Algorithm Based PRAM/DRAM Hybrid Memory Allocation Optimization
    Wu, Yizhi
    Zhang, Guo
    Zhang, Youtao
    PROCEEDINGS OF THE 2013 ASIA-PACIFIC COMPUTATIONAL INTELLIGENCE AND INFORMATION TECHNOLOGY CONFERENCE, 2013, : 744 - 749
  • [10] AN EXPERIMENTAL SINGLE-CHIP DATA FLOW CPU
    UVIEGHARA, GA
    HWU, WMW
    NAKAGOME, Y
    JEONG, DK
    LEE, DD
    HODGES, DA
    PATT, YN
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (01) : 17 - 28