Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process

被引：12

作者：

Ker, MD ^{[1
]}

Hung, KK ^{[1
]}

Tang, HTH ^{[1
]}

Huang, SC ^{[1
]}

Chen, SS ^{[1
]}

Wang, MC ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Integrated Circuits & Syst Lab, Hsinchu, Taiwan

来源：

PROCEEDINGS OF THE 2001 8TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS | 2001年

关键词：

D O I：

10.1109/IPFA.2001.941462

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：91 / 96

页数：6

共 10 条

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[5] Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process [J].

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[6]

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[7]

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[8] EOS/ESD reliability of partially depleted SOI technology [J].

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[9]

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[10]

VOLDMAN S, 1996, P EOS ESD S, P291

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