220mV-900mV 794/584/754 Gbps/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14nm Tri-gate CMOS

被引：0

作者：

Satpathy, Sudhir ^{[1
]}

Suresh, Vikram ^{[1
]}

Mathew, Sanu ^{[1
]}

Anders, Mark ^{[1
]}

Kaul, Himanshu ^{[1
]}

Agarwal, Amit ^{[1
]}

Hsu, Steven ^{[1
]}

Krishnamurthy, Ram ^{[1
]}

机构：

[1] Intel Corp, Circuits Res Lab, Hillsboro, OR 97124 USA

来源：

2018 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A reconfigurable AES/SMS4/Camellia symmetric-key cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25 degrees C. Hybrid GF(2(4))(2) Sbox-based unified datapath with in-line key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with key-precompute, and shared round constant circuits result in a 9152 mu m(2) design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV.

引用

页码：175 / 176

页数：2

共 6 条

[1] High-Throughput Area-Efficient Processor for Cryptography
Huo Yuanhong
Liu Dake
[J]. CHINESE JOURNAL OF ELECTRONICS, 2017, 26 (03) : 514 - 521
[2] Jan C-H, 2015, VLSI TECH S, P12
[3] 340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(24)2 Polynomials in 22 nm Tri-Gate CMOS
Mathew, Sanu
Satpathy, Sudhir
Suresh, Vikram
Anders, Mark
Kaul, Himanshu
Agarwal, Amit
Hsu, Steven
Chen, Gregory
Krishnamurthy, Ram
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (04) : 1048 - 1058
[4] Satpathy S, 2016, VLSI CIRC S, P244
[5] Zhang Y., 2016, VLSI CIRC S, P246
[6] Zhang Y, 2017, VLSI CIRC S, P265

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