Novel thin sidewall structure for high performance bulk CMOS with charge-assisted source-gain-extension

被引：6

作者：

Ohta, H. ^{[1
]}

Fukutome, H. ^{[1
]}

Sakuma, T. ^{[1
]}

Hatada, A. ^{[1
]}

Ohkoshi, K. ^{[2
]}

Ikeda, K. ^{[1
]}

Miyashita, T. ^{[1
]}

Mori, T. ^{[2
]}

Sugii, T. ^{[1
]}

机构：

[1] Fujitsu Labs Ltd, 50 Fuchigami, Tokyo 1970833, Japan

[2] Fujitsu Ltd, Tokyo, Japan

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339751

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a novel junction profile engineering using thin sidewall structure and applied it to sub-40 nm uniaxial strained CMOS devices. This transistor used a high-k thin sidewall with electrical charge in achieving a higher drive current with keeping the short channel effect. Consequently, the 18.5/15.6 % reduction of parasitic resistance achieve the 8.2/13.0 % improvement in the saturation current (I-on) at 38 nm gate length for nMOS and pMOS. In addition, I-on dependence on active width (W.) for pMOS is very small. In the size of active width : 0.1 mu m, a 42 % of I-on enhancement gave us I-on=680 mu A/mu m at V-dd=1 V. These characteristics are originated from formation of inversion layer and suppressing channeling penetration of pocket impurities implanted. A high performance Bulk nMOS and pMOS were demonstrated with I-on of 1069 mu A/mu m and 725 mu A/mu m at V-dd=1 V / I-off=100 nA/mu m, respectively.

引用

页码：120 / +

页数：2

共 6 条

[1]

[Anonymous], 2003, IEEE INT ELECT DEVIC

[2]

Fukutome H, 2005, 2005 Symposium on VLSI Technology, Digest of Technical Papers, P140

[3] 50 nm MOSFET with electrically induced source/drain (S/D) extensions [J].