An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-design (Invited Paper)

被引:6
|
作者
Liu, Mingshuo [1 ]
Luo, Shiyi [1 ]
Han, Kevin [1 ]
Yuan, Bo [2 ]
DeMara, Ronald F. [3 ]
Bai, Yu [1 ]
机构
[1] Calif State Univ Fullerton, Fullerton, CA 92634 USA
[2] Rutgers State Univ, New Brunswick, NJ USA
[3] Univ Cent Florida, Orlando, FL 32816 USA
来源
2021 IEEE 32ND INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2021) | 2021年
基金
美国国家科学基金会;
关键词
Deep learning; FPGA; Tensor Train; Energy Efficiency; RECURRENT NEURAL-NETWORKS;
D O I
10.1109/ASAP52443.2021.00020
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The fast development of object detection techniques has attracted attention to developing efficient Deep Neural Networks (DNNs). However, the current state-of-the-art DNN models can not provide a balanced solution among accuracy, speed, and model size. This paper proposes an efficient real-time object detection framework on resource-constricted hardware devices through hardware and software co-design. The Tensor Train (TT) decomposition is proposed for compressing the YOLOv5 model. By unitizing the unique characteristics given by the TT decomposition, we develop an efficient hardware accelerator based on FPGA devices. Experimental results show that the proposed method can significantly reduce the model size and improve the execution time.
引用
收藏
页码:77 / 84
页数:8
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