A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator

被引：82

作者：

Kreienkamp, R ^{[1
]}

Langmann, U ^{[1
]}

Zimmermann, C ^{[1
]}

Aoyama, T ^{[1
]}

Siedhoff, H ^{[1
]}

机构：

[1] Ruhr Univ Bochum, D-44780 Bochum, Germany

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2005年 / 40卷 / 03期

关键词：

analog quadrature phase interpolator; chip-to-chip interconnects; CMOS; half-rate clock and data recovery;

D O I：

10.1109/JSSC.2005.843624

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-mu m CMOS technology the module has a size of 0.25 x 1.4 mm(2). The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2(23)-1 and a bit-error rate threshold. of 10(-12). The retimed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.

引用

页码：736 / 743

页数：8

共 17 条

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